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Table 1.2.1 Features of the M32R Family CPU Core
Functional Block
M32R family
CPU core
Table 1.2.2 Features of Internal Memory
Functional Block
RAM
Flash memory
Features
• Bus specifications
Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock)
Logical address space: 4Gbytes, linear
Extended external area: Maximum 4 Mbytes
External data bus: 16 bits
• Implementation: Five-stage pipeline
• Internal 32-bit architecture for the core
• Register configuration
General-purpose register: 32 bits × 16 registers
Control register: 32 bits × 5 registers
• Instruction set
16-bit and 32-bit instruction formats
83 distinct instructions and 9 addressing modes
• Built-in multiplier/accumulator (32 × 16 + 56)
Features
• Capacity
M32170F6 : 40 Kbytes
M32170F4, M32170F3 : 32 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• By using RTD (real-time debugger), the internal RAM can be accessed for read or
rewrite from external devices independently of the M32R.
• Capacity
M32170F6 : 768 Kbytes
M32170F4 : 512 Kbytes
M32170F3 : 384 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• Durability: Can be rewritten 100 times
1-8
OVERVIEW
1.2 Block Diagram
Ver.0.10
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