Typical Csio Receive Operation - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

12.4.6 Typical CSIO Receive Operation

The following shows a typical receive operation in CSIO mode.

Receive clock

Receive enable bit

Receive status bit

Receive-finished bit

SIO receive interrupt

(When receive-finished

interrupt is selected)

(When receive error

interrupt is selected)

Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit

Note 2 : When receive-finished interrupt is enabled (DMA transfer can also be requested at the same

Note 3 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register"

interrupt request bit cleared

Figure 12.4.3 Example of CSIO Reception (When Received Normally)

Internal clock selected

Set by a write to

transmit buffer

: Processing by software

12.4 Receive Operation in CSIO Mode

External clock selected

Receive-finished interrupt

No interrupt request

: Interrupt generation

Clock stopped

Automatically

cleared for each

receive operation

Read from receive buffer

Interrupt request accepted