Functional Description Of The Dmac; Cause Of Dma Request - Mitsubishi Electric M32R Series User Manual

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9.3 Functional Description of the DMAC

9.3.1 Cause of DMA Request

For each DMA channel (channels 0 to 9), DMA transfer can be requested from multiple sources.
There are various causes (or sources) of DMA transfer, so that DMA transfer can be started by a
request from internal peripheral I/O, started in software by a program, or can be started upon
completion of one transfer or all transfers in a DMA channel (cascade mode).
The cause of DMA request is selected using the cause of request select bit provided for each
channel, REQSLn (DMAn Channel Control Register bits D2, D3). The table below lists the causes
of DMA requests in each channel.
Table 9.3.1 Causes of DMA Requests in DMA0 and Generation Timings
REQSL0 Cause of DMA Request
0 0 Software start
or one DMA2 transfer completed
0 1 A-D0 conversion completed
1 0 MJT (TIO8_udf)
1 1 MJT (input event bus 2)
Table 9.3.2 Causes of DMA Requests in DMA1 and Generation Timings
REQSL1 Cause of DMA Request
0 0 Software start
0 1 MJT (output event bus 0)
1 0 MJT (TIN13 input signal)
1 1 One DMA0 transfer completed
9.3 Functional Description of the DMAC
DMA Request Generation Timing
When any data is written to DMA0 Software Request
Generation Register (software start)
or one DMA2 transfer is completed (cascade mode)
When A-D0 conversion is completed
When MJT TIO8 underflow occurs
When MJT's input event bus 2 signal is generated
DMA Request Generation Timing
When any data is written to DMA1 Software Request
Generation Register
When MJT's output event bus 0 signal is generated
When MJT's TIN13 input signal is generated
When one DMA0 transfer is completed (cascade mode)
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DMAC
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