Processing Of Internal Peripheral I/O Interrupts By Handlers - Mitsubishi Electric M32R Series User Manual

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5.5.2 Processing of Internal Peripheral I/O Interrupts by Handlers

(1) Branching to the interrupt handler
When the CPU accepts an interrupt, control branches to the EIT vector entry after hardware
preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for
External Interrupt (EI) is located at address H'0000 0080. This address is where the instruction
(not the jump address) for branching to the beginning of the interrupt processing routine for
External Interrupt (EI) is written.
(2) Processing by interrupt handler
In the External Interrupt (EI) handler, first save the BPC register, PSW register, and general-
purpose registers to the stack.
Next, read out the Interrupt Mask Register (IMASK) and save the read value to the stack. Then
read out the Interrupt Vector Register (IVECT). Always be sure to read out the IMASK before
reading the IVECT. A read of IMASK and that of IVECT both triggers an operation to clear
interrupt requests to the CPU and accept the next interrupt. Furthermore, a read of IVECT
causes NEW_IMASK to be set in the IMASK and the accepted interrupt request to be cleared
(not cleared in the case of level-recognized interrupt sources, however).
The IVECT register has set in it the 16 low-order bits of ICU vector table address for the accepted
interrupt source. Read the IVECT register using a signed halfword load instruction (LDH
instruction) and then the content of the ICU interrupt vector table indicated by the read address.
Make sure the ICU vector table has the start addresses of interrupt handlers for each internal
peripheral I/O written in it beforehand, so that control will branch to the address read from this
table to execute processing by each handler.
When returning from the handler, clear the PSW register IE bit to 0 to disable interrupts and then
restore the IMASK value from the stack.
(3) Identifying the source of interrupt generated
If any internal peripheral I/O has multiple interrupt sources, check the Interrupt Status Register
for each internal peripheral I/O to identify the source of interrupt generated.
(4) Enabling multiple interrupts
To enable another interrupt in an interrupt handler, set the PSW register's IE (Interrupt Enable)
bit to 1 to enable interrupts so that they will be accepted. However, before writing a 1 to the IE bit,
always be sure to save each register (BPC, PSW, general-purpose register, and IMASK) to the
stack.
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
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