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10
10.6.6 TML Measure Registers
TML0 Measure 3 Register (TML0MR3H)
TML0 Measure 3 Register (TML0MR3L)
TML0 Measure 2 Register (TML0MR2H)
TML0 Measure 2 Register (TML0MR2L)
TML0 Measure 1 Register (TML0MR1H)
TML0 Measure 1 Register (TML0MR1L)
TML0 Measure 0 Register (TML0MR0H)
TML0 Measure 0 Register (TML0MR0L)
D0
1
2
D0
1
2
D
Bit Name
0-15
TML0MR3H-0H
TML0MR3L-0L
Note 1: These registers are a read-only register.
Note 2: These registers must always be accessed in words (32 bits) beginning with a word boundary.
The TML0 Measure Registers are used to latch counter contents upon event input. The TML0
Measure Registers are configured with 32 bits, the TML0MR3H-0H accommodating the 16 high-
order bits, and the TML0MR3L-0L accommodating the 16 low-order bits. The TML0 Measure
Registers are a read-only register. These registers must always be accessed in words (32 bits)
beginning with a word boundary.
3
4
5
6
TML0MR3H-TML0MR0H (16 high-order bits)
3
4
5
6
TML0MR3L-TML0MR0L (16 low-order bits)
10-156
MULTIJUNCTION TIMERS
10.6 TML (Input-related 32-bit Timer)
7
8
9
10
11
7
8
9
10
11
Function
32-bit counter value (16 high-order bits)
32-bit counter value (16 low-order bits)
<Address: H'0080 03F0>
<Address: H'0080 03F2>
<Address: H'0080 03F4>
<Address: H'0080 03F6>
<Address: H'0080 03F8>
<Address: H'0080 03FA>
<Address: H'0080 03FC>
<Address: H'0080 03FE>
12
13
14
D15
12
13
14
D15
<When reset: Indeterminate>
R
Ver.0.10
W
–
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