Power-Shutdown Sequence When Using Ram Backup - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers
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20.3.2 Power-Shutdown Sequence When Using RAM Backup

The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/
E when using RAM backup.
VCCE
AVCC0,
AVCC1
VREF0,
VREF1
5V
P72 / HREQ
5V
RESET
3.3V
VDD
3.3V
VCCI
3.3V
FVCC
3.3V
OSC-VCC
__________
:
Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in
software. The M32R/E allows P72 to be used as HREQ irrespective of its operation mode.
:
With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull
____________
the RESET pin input low.
:
Turn off the 5 V and the 3.3 V power supply after the RESET pin goes low.
: Reduce the VDD voltage from 3.3 V to 2.0 V as necessary.
Note: Power-shutdown requirements
• VDD
• OSC-VCC
Figure 20.3.2 Power-Shutdown Sequence When Using RAM Backup
1
2
____________
VCCI
FVCC
VCCI
20-6
5V
5V
5V
3
4
2.0V
3
____________
0V
0V
0V
0V
0V
0V
0V
0V
Ver.0.10

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