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10
10.9.3 TOM Related Register Map
The diagram below shows a TOM related register map.
H'0080 0C90
H'0080 0C92
H'0080 0C94
H'0080 0C96
H'0080 0C98
H'0080 0C9A
H'0080 0C9C
H'0080 0C9E
H'0080 0CA0
H'0080 0CA2
H'0080 0CA4
H'0080 0CA6
H'0080 0CA8
H'0080 0CAA
H'0080 0CAC
H'0080 0CAE
H'0080 0CB0
H'0080 0CB2
H'0080 0CB4
H'0080 0CB6
H'0080 0CB8
H'0080 0CBA
H'0080 0CBC
H'0080 0CBE
Blank addresses are reserved.
Note: The registers enclosed in thick frames must always be accessed
Figure 10.9.2 TOM Related Register Map (1/2)
Address
+0 Address
D0
in halfwords.
10.9 TOM (Output-related 16-bit Timer)
D7 D8
TOM0_0 Counter (TOM00CT)
TOM0_0 Reload 1 Register (TOM00RL1)
TOM0_0 Reload 0 Register (TOM00RL0)
TOM0_1 Counter (TOM01CT)
TOM0_1 Reload 1 Register (TOM01RL1)
TOM0_1 Reload 0 Register (TOM01RL0)
TOM0_2 Counter (TOM02CT)
TOM0_2 Reload 1 Register (TOM02RL1)
TOM0_2 Reload 0 Register (TOM02RL0)
TOM0_3 Counter (TOM03CT)
TOM0_3 Reload 1 Register (TOM03RL1)
TOM0_3 Reload 0 Register (TOM03RL0)
TOM0_4 Counter (TOM04CT)
TOM0_4 Reload 1 Register (TOM04RL1)
TOM0_4 Reload 0 Register (TOM04RL0)
TOM0_5 Counter (TOM05CT)
TOM0_5 Reload 1 Register (TOM05RL1)
TOM0_5 Reload 0 Register (TOM05RL0)
10-207
MULTIJUNCTION TIMERS
+1 Address
D15
Ver.0.10
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