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11
11.3.2 A-D Conversion by Successive Approximation Method
The A-D converter has A-D convert operation started by an A-D conversion start trigger (in software
or hardware). Once A-D conversion begins, the following operation is automatically executed.
During single mode, Single Mode Register 0's A-D conversion/comparate completion bit is
cleared to 0. During scan mode, Can Mode Register 0's A-D conversion completion bit is
cleared to 0.
The content of the A-D Successive Approximation Register is cleared to "H'0000."
The A-D Successive Approximation Register's most significant bit (D6) is set to 1.
The comparison voltage, Vref(note), is fed from the D-A converter into the comparator.
The comparison voltage, Vref, and the analog input voltage, VIN, are compared, with the
comparison result stored in D6.
Operations in steps
The value stored in the A-D Successive Approximation Register at completion of the
comparison of D15 is the final A-D conversion result.
1st comparison
2nd comparison
3rd comparison
10th comparison
Conversion
completed
Figure 11.3.2 Changes of the A-D Successive Approximation Register during A-D Convert Operation
Note: The comparison voltage, Vref (the voltage fed from the D-A converter into the comparator), is
determined according to changes of the content of the A-D Successive Approximation Register. Shown
below are the equations used to calculate the comparison voltage, Vref.
• When the content of the A-D Successive Approximation Register = 0
Vref [V] = 0
• When the content of the A-D Successive Approximation Register = 1 to 1,023
Vref [V] = (reference voltage VREF / 1,024) x (content of the A-D Successive Approximation Register - 0.5)
If Vref < VIN, then D6 = 1
If Vref > VIN, then D6 = 0
through
above are executed for all other bits from D7 to D15.
A-D Successive Approximation Register (ADiSAR)
D6
7
8
9
1
0
0
0
n9
1
0
0
Result of 1st comparison
n9
n8
1
0
Result of 2nd comparison
n9
n8
n7
n6
n9
n8
n7
n6
11-42
11.3 Functional Description of A-D Converters
10
11
12
13
14 D15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
n5
n4
n3
n2
n1
n5
n4
n3
n2
n1
A-D CONVERTERS
i=0,1
0
Vref > VIN then nX=0
0
Vref < VIN then nX=1
0
1
n0
Ver.0.10
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