Mitsubishi Electric M32R Series User Manual page 526

11
(1) ADnCMSL (A-Dn scan mode selection) bit (D1)
This bit selects scan mode of the A-Dn converter between single-shot scan and continuous scan.
Setting this bit to 0 selects single-shot scan mode, so that the channels selected by the
ANnSCAN (scan loop selection) bits are sequentially A-D converted and when A-D conversion in
all selected channels are completed, the conversion operation stops.
Setting this bit to 1 selects continuous scan mode, so that when operation in single-shot scan
mode is completed, the selected channels are A-D converted beginning with the first channel
again. This A-D conversion is continued until halted by setting the ADnCSTP (A-Dn conversion
stop) bit to 1.
(2) ADnCTRG (A-Dn hardware trigger selection) bit (D2)
When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use
external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/
underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL
(A-Dn conversion start trigger selection) bit is set to choose a software trigger. When using the
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ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input
is held low, new A-D conversion is not started.
(3) ADnCSEL (A-Dn conversion start trigger selection) bit (D3)
This bit selects whether to use a software or hardware trigger to start A-D conversion of the A-Dn
converter during scan mode. When you choose a software trigger, A-D conversion is started by
setting the ADnCSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D
conversion is started for the cause of start selected by the ADnCTRG (hardware trigger
selection) bit.
(4) ADnCREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4)
For the A-D0 converter (AD0SCM0), this bit selects whether to request an A-D0 conversion
interrupt or DMA transfer when one cycle of scan operation is completed. For the A-D1 converter
(AD1SCM0), this bit selects whether to enable or disable an A-D0 conversion interrupt when one
cycle of scan operation is completed.
(5) ADnCCMP (A-Dn conversion completion) bit (D5)
This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing
scan mode A-D conversion and set to 1 when single-shot scan mode is completed, or when
continuous scan mode is halted by setting ADnCSTT (A-Dn conversion stop) bit to 1.
11.2 A-D Converter Related Registers
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A-D CONVERTERS
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Ver.0.10