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10.6.7 Operation of TML Measure Input
(1) Outline of TML measure input
In TML measure input, the counter starts counting up clock pulses upon deassertion of reset.
When event input is entered to measure registers 0-3, the counter value is latched into the
measure registers.
A TIN interrupt can be generated by entering an external measure signal. (No TML counter
overflow interrupts are available.)
Count clock
Reset
H'FFFF FFFF
Counter (32 bits)
Indeterminate
value
H'0000 0000
Measure 0 register
TIN23 interrupt
Measure 1 register
TIN22 interrupt
Figure 10.6.3 Typical Operation in TML Measure Input
Enabled
Measure
(by deassertion
event 0
of reset)
occurs
Initial value (indeterminate)
Initial value (indeterminate)
Note: This diagram does not show detail timing information.
10-158
MULTIJUNCTION TIMERS
10.6 TML (Input-related 32-bit Timer)
Measure
Overflow
event 1
occurs
occurs
H'C000 0000
H'8000 0000
H'8000 0000
H'C000 0000
Measure
Measure
event 0
event 1
occurs
occurs
H'D000 0000
H'6000 0000
H'6000 0000
H'D000 0000
Ver.0.10