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10
Count clock
Enable bit
Write to
correction register
H'FFFF
Counter
H'0000
Reload register
Correction register
F/F output
TOP interrupt
due to underflow
Note: This diagram does not show detail timing information.
Figure 10.3.18 Typical Operation in TOP Delayed Single-shot Output Mode when Correction
Applied
Underflow
(first time)
H'(F000+0008+1)
H'F000
H'A000
H'F000
Indeterminate
Data inverted by
underflow
10-94
MULTIJUNCTION TIMERS
10.3 TOP (Output-related 16-bit Timer)
Counter corrected
H'0008
Underflow
(second time)
Data inverted by
underflow
Ver.0.10
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