Mitsubishi Electric M32R Series User Manual page 519

11
(1) ADnSTRG (A-Dn hardware trigger selection) bit
When starting A-D conversion of the A-Dn converter in hardware, this bit selects whether to use
external ADTRG signal input or MJT output (output event bus 3 for A-D0, or TID1 overflow/
underflow for A-D1) to start the operation. The content of this bit is ignored when the ADnSSEL
(A-Dn conversion start trigger selection) bit is set to choose a software trigger. When using the
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ADTRG pin for a start trigger, not that if A-D conversion is completed while the ADTRG pin input
is held low, new A-D conversion is not started.
(2) ADnSSEL (A-Dn conversion start trigger selection) bit (D3)
This bit selects whether to use a software or hardware trigger to start A-Dn conversion during
single mode. When you choose a software trigger, A-D conversion is started by setting the
ADnSSTT (A-Dn conversion start) bit to 1. When you choose a hardware trigger, A-D conversion
is started for the cause of start selected by the ADnSTRG (hardware trigger selection) bit.
(3) ADnSREQ (A-Dn interrupt request/DMA transfer request selection) bit (D4)
For the A-D0 converter (AD0SIM0), this bit selects whether to request an A-D0 conversion
interrupt or DMA transfer when single mode operation (A-D conversion or comparate) is
completed. For the A-D1 converter (AD1SIM0), this bit selects whether to enable or disable an A-
D0 conversion interrupt when single mode operation (A-D conversion or comparate) is
completed.
(4) ADnSCMP (A-Dn conversion/comparate completion) bit (D5)
This is a read-only bit, which when reset is 1. This bit is 0 when the A-Dn converter is performing
single mode operation (A-D conversion or comparate) and set to 1 when the operation is
completed. This bit also is set to 1 when A-D conversion or comparate operation is forcibly
terminated by setting the ADnSSTT (A-Dn conversion stop) bit to 1 during A-D conversion or
comparate operation.
(5) ADnSSTP (A-Dn conversion stop) bit (D6)
Single mode operation (A-D conversion or comparate) of the A-Dn converter can be halted by
setting this bit to 1 while the operation is in progress. Manipulation of this bit is ignored when
single mode is idle or when scan mode operation is under way. Operation is halted immediately
by a write to this bit, and when you read the A-Dn Successive Approximation Register after being
halted, the content you get is the value in the middle of conversion. (Not transferred to the A-Dn
Data Register.)
If the A-Dn conversion start bit and A-Dn conversion stop bit are set to 1 at the same time, the A-
Dn conversion stop bit has priority.
If this bit is set to 1 while operating in single mode during special mode "Forcible single mode
execution during scan mode," only single mode conversion is halted and scan mode operation is
restarted.
11.2 A-D Converter Related Registers
(D2)
11-21
A-D CONVERTERS
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Ver.0.10