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10
10.6.5 TML Counters
TML0 Counter, High (TML0CTH)
TML0 Counter, Low (TML0CTL)
D0
1
2
D0
1
2
D
Bit Name
0-15
TML0CTH
TML0CTL
Note: This register must always be accessed in words (32 bits) beginning with the address of TML0CTH.
The TML0 Counter is a 32-bit up-counter, which starts counting upon deassertion of reset. The
TML0CTH register accommodates the 16 high-order bits, and the TML0CTL register
accommodates the 16 low-order bits of the 32-bit counter.
The counter can be read on-the-fly.
3
4
5
6
TML0CTH (16 high-order bits)
3
4
5
6
TML0CTL (16 low-order bits)
10-154
MULTIJUNCTION TIMERS
10.6 TML (Input-related 32-bit Timer)
7
8
9
10
11
7
8
9
10
11
Function
32-bit counter value (16 high-order bits)
32-bit counter value (16 low-order bits)
<Address: H'0080 03E0>
<Address: H'0080 03E2>
12
13
14
D15
12
13
14
D15
<When reset: Indeterminate>
R
Ver.0.10
W
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