Mitsubishi Electric M32R Series User Manual page 258

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Table 9.3.3 Causes of DMA Requests in DMA2 and Generation Timings
REQSL2 Cause of DMA Request
0 0 Software start
0 1 MJT (output event bus 1)
1 0 MJT (TIN18 input signal)
1 1 One DMA1 transfer completed
Table 9.3.4 Causes of DMA Requests in DMA3 and Generation Timings
REQSL3 Cause of DMA Request
0 0 Software start
0 1 Serial I/O0 (transmit buffer empty)
1 0 Serial I/O1 (reception completed)
1 1 MJT (TIN0 input signal)
Table 9.3.5 Causes of DMA Requests in DMA4 and Generation Timings
REQSL4 Cause of DMA Request
0 0 Software start
0 1 One DMA3 transfer completed
1 0 Serial I/O0 (reception completed)
1 1 MJT (TIN19 input signal)
9.3 Functional Description of the DMAC
DMA Request Generation Timing
When any data is written to DMA2 Software Request
Generation Register
When MJT's output event bus 1 signal is generated
When MJT's TIN18 input signal is generated
When one DMA1 transfer is completed (cascade mode)
DMA Request Generation Timing
When any data is written to DMA3 Software Request
Generation Register
When serial I/O0 transmit buffer is emptied
When serial I/O1 reception is completed
When MJT's TIN0 input signal is generated
DMA Request Generation Timing
When any data is written to DMA4 Software Request
Generation Register
When one DMA3 transfer is completed (cascade mode)
When serial I/O0 reception is completed
When MJT's TIN19 input signal is generated
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DMAC
Ver.0.10