Mitsubishi Electric M32R Series User Manual page 592

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

Transmit clock

Receive enable bit

Receive-finished bit

Overrun error bit

SIO receive interrupt

(When receive-finished

interrupt is selected)

(When receive error

interrupt is selected)

Note 1 : Change of the Interrupt Controller "SIO Receive Interrupt Control Register" interrupt request bit

Note 2 : When receive-finished interrupt is enabled

Note 3 : When receive error interrupt is enabled

Note 4 : Receive enable bit cleared

Note 5 : The Interrupt Controller IVECT register is read or "SIO Receive Interrupt Control Register"

interrupt request bit cleared

Figure 12.4.4 Example of CSIO Reception (When Overrun Error Occurred)

Internal clock selected

Receive-finished interrupt

: Processing by software

12.4 Receive Operation in CSIO Mode

External clock selected

First data reception

Next data reception

Receive buffer not read

during this interval

Interrupt request accepted (Note 5)

Receive error interrupt

Interrupt request accepted (Note 5)

: Interrupt generation

Overrun error bit cleared