Starting Csio Reception; Processing At End Of Csio Reception - Mitsubishi Electric M32R Series User Manual

Mitsubishi 32-bit risc single-chip microcomputers

Table of Contents

12.4.2 Starting CSIO Reception

When all of the following receive conditions are met after you finished initialization, the serial I/O

starts receive operation.

(1) Receive conditions when CSIO mode internal clock is selected

• The SIO Receive Control Register's receive enable bit is set to 1.

• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.")

(2) Receive conditions when CSIO mode external clock is selected

• The SIO Receive Control Register's receive enable bit is set to 1.

• Transmit conditions are met. (Refer to Section 12.3.3, "Starting CSIO Transmission.")

Note : The receive status bit is set to 1 at the time dummy data is set in the lower byte of the SIO

Transmit Buffer Register.

When the above conditions are met, the serial I/O starts receiving 8-bit serial data (LSB first)

synchronously with the receive shift clock.

When data reception is completed, the following operation is automatically performed in hardware.

(1) When reception is completed normally

The receive-finished (receive buffer full) bit is set to 1.

Note 1 : If a receive-finished (receive buffer full) interrupt has been enabled, an interrupt request

is generated.

Note 2 : A DMA transfer request is generated.

(2) When error occurs during reception

When an error (only overrun error in CSIO mode) occurs during reception, the overrun error bit

and receive sum bit are set to 1.

Note 1 : If a receive-finished interrupt has been selected (by SIO Cause of Receive Interrupt

Select Register), neither a receive-finished interrupt request nor a DMA transfer request

is generated.

Note 2 : If a receive error interrupt has been selected (by SIO Cause of Receive Interrupt Select

enabled. No DMA transfer requests are generated.

12.4 Receive Operation in CSIO Mode