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9
9.2.5 DMA Transfer Count Registers
DMA0 Transfer Count Register (DM0TCT)
DMA1 Transfer Count Register (DM1TCT)
DMA2 Transfer Count Register (DM2TCT)
DMA3 Transfer Count Register (DM3TCT)
DMA4 Transfer Count Register (DM4TCT)
DMA5 Transfer Count Register (DM5TCT)
DMA6 Transfer Count Register (DM6TCT)
DMA7 Transfer Count Register (DM7TCT)
DMA8 Transfer Count Register (DM8TCT)
DMA9 Transfer Count Register (DM9TCT)
D8
D
Bit Name
8 - 15
DM0TCT - DM9TCT
The DMA Transfer Count Register is used to set the number of times data is transferred in each
channel. However, the value in this register is ignored during ring buffer mode.
The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer
Count Register is comprised of a current register, the value you get by reading this register is
always the current value. (However, if you read this register in a cycle immediately after transfer,
the value you get is the value that was in the count register before the transfer began.) When
transfer finishes, this count register underflows, so that the read value you get is H'FF.
If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or
when all transfers are completed (at which the transfer count register underflows), transfer in the
cascaded channel starts.
9
10
11
DM0TCT - DM9TCT
Function
DMA transfer count
(ignored during 32-channel ring buffer mode)
9-20
9.2 DMAC Related Registers
<Address: H'0080 0411>
<Address: H'0080 0421>
<Address: H'0080 0431>
<Address: H'0080 0441>
<Address: H'0080 0451>
<Address: H'0080 0419>
<Address: H'0080 0429>
<Address: H'0080 0439>
<Address: H'0080 0449>
<Address: H'0080 0459>
12
13
14
<When reset : Indeterminate>
DMAC
D15
R
W
Ver.0.10
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