Gbe Mac Interface Guidelines; Frequency Requirements; Gigabit Ethernet Interface Signals; Gbe Controller/Lan Interface Interconnect - Intel EP80579 Manual

Gigabit Ethernet (GbE) Interface—Intel
19.2

GbE MAC Interface Guidelines

The GbE design guidelines provided in this chapter apply only to the interface between
the GbE MAC interface and the LAN PHY component. See the LAN component's
documentation for design guidelines, magnetics module and the Physical Interface
Connector (See
Figure 135. GbE Controller/LAN Interface Interconnect
EP80579
GbE
MAC
19.3

Frequency Requirements

Table 79
Table 79.

Frequencies of All Input Clocks

Model
RMII
RGMII
19.4

Gigabit Ethernet Interface Signals

GbE Port0 supports Wake-On-LAN (WOL) hence the GbE Port0 block resides in the
Sustain Voltage rail within EP80579
interface signals on the platform be powered with GbE Standby Voltage. GbE Port 1&2
signals are to be powered with the GbE core power voltages.
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Figure 135).
TX data/
GbE LAN
control
Interface
RX data/
(PHY)
control
provides the frequency of all input clocks in the different modes of operation:
Clock Name
GBE_REFCLK 50 MHz ± 50 ppm
GBE_REFCLK_RMII 50 MHz ± 50 ppm
GBEn_RxCLK 2.5/25/125 MHz
GBE_REFCLK 125 MHz± 50 ppm
Magnetics
Module
Frequency
It is required that all GbE Port0 (Transmit/Receive)
.
Connector
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