Xilinx LogiCORE IP AXI Product Manual page 84

X-Ref Target - Figure 5-2
Table 5-1 provides a descriptions of the contents of the example design directories.
Table 5-1: Example Design Structure
project_1/axi_pcie_0_example
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/imports/
example_design/
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/ip/axi_pcie_0
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sources_1/ip/
axi_bram_ctrl_0
project_1/axi_pcie_0_example/
axi_pcie_0_example.srcs/sim_1/imports/
simulation/dsport
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 5-2: Example Design Output Structure
Directory
www.xilinx.com
Chapter 5: Example Design
Description
Contains all example design files.
Contains the top module for the
example design,
xilinx_axi_pcie_ep.v.
Contains the XDC file based on device
selected, all design files and subcores
used in axi_pcie, and the top modules for
simulation and synthesis.
Contains block RAM controller files used
in example design.
Contains all RP files, cgator and PIO files.
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