Xilinx LogiCORE IP AXI Product Manual page 100

Debugging PCI Configuration Space Parameters
Often, a user application fails to be recognized by the system, but the Xilinx PIO Example
design works. In these cases, the user application is often using a PCI configuration space
setting that is interfering with the system systems ability to recognize and allocate
resources to the card.
The Xilinx solutions for PCI Express handle all configuration transactions internally and
generate the correct responses to incoming configuration requests. Chipsets have limits to
the amount of system resources they can allocate and the core must be configured to
adhere to these limitations.
The resources requested by the Endpoint are identified by the BAR settings within the
Endpoint configuration space. You should verify that the resources requested in each BAR
can be allocated by the chipset. I/O BARs are especially limited so configuring a large I/O
BAR typically prevents the chipset from configuring the device. Generate a core that
implements a small amount of memory (approximately 2 KB) to identify if this is the root
cause.
The Class Code setting selected in the Vivado IDE can also affect configuration. The Class
Code informs the Chipset as to what type of device the Endpoint is. Chipsets might expect
a certain type of device to be plugged into the PCI Express slot and configuration might fail
if it reads an unexpected Class Code. The BIOS could be configurable to work around this
issue.
Using a link analyzer, it is possible to monitor the link traffic and possibly determine when
during the enumeration and configuration process problems occur.
Using a Link Analyzer to Debug Device Recognition Issues
In cases where the link is up (user_lnk_up = 1), but the device is not recognized by the
system, a link analyzer can help solve the issue. It is likely the FPGA is not responding
properly to some type of access. The link view can be used to analyze the traffic and see if
anything looks out of place.
To focus on the issue, it might be necessary to try different triggers. Here are some trigger
examples:
• Trigger on the first INIT_FC1 and/or UPDATE_FC in either direction. This allows the
analyzer to begin capture after link up.
• The first TLP normally transmitted to an Endpoint is the Set Slot Power Limit Message.
This usually occurs before Configuration traffic begins. This might be a good trigger
point.
• Trigger on Configuration TLPs.
• Trigger on Memory Read or Memory Write TLPs.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
www.xilinx.com
Appendix B: Debugging
100
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