Xilinx LogiCORE IP AXI Product Manual page 18

Table 2-4: Top-Level Parameters (Cont'd)
Generic Parameter Name
C_AXIBAR_
G28
HIGHADDR_5
G29 C_AXIBAR_AS_5
G30 C_AXIBAR2PCIEBAR_5
G31 C_PCIEBAR_NUM
G32 C_PCIEBAR_AS
G33 C_PCIEBAR_LEN_0
G34 C_PCIEBAR2AXIBAR_0
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
AXI BAR_5 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_5 address
size
1: 64 bit
PCIe BAR to which
AXI BAR_5 is Valid address for PCIe
mapped
1-3;
1: BAR_0 enabled
Number of address
for PCIe apertures
2: BAR_0, BAR_1 enabled
that can be accessed
3: BAR_0, BAR_1, BAR_2
enabled
0: Generates three 32-bit
PCIEBAR address
apertures.
32-bit BAR example:
PCIEBAR_0 is 32 bits
PCIEBAR_1 is 32 bits
PCIEBAR_2 is 32 bits
1: Generates three 64 bit
PCIEBAR address
Configures PCIEBAR
apertures.
aperture width to be
64-bit BAR example:
32 bits wide or 64
PCIEBAR_0 and PCIEBAR_1
bits wide
concatenate to comprise
64-bit PCIEBAR_0.
PCIEBAR_2 and PCIEBAR_3
concatenate to comprise
64-bit PCIEBAR_1.
PCIEBAR_4 and PCIEBAR_5
concatenate to comprise
64-bit PCIEBAR_2
Power of 2 in the
size of bytes of PCIE 13-31
BAR_0 space
AXIBAR to which
PCIE BAR_0 is Valid AXI address
mapped
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Chapter 2: Product Specification
Allowable Values Default Value VHDL Type
(1)(3)(4)
0x0000_0000
(2)
0xFFFF_FFFF
0x0000_0000
std_logic_
vector
0 Integer
std_logic_
vector
3 Integer
1 Integer
16 Integer
std_logic_
vector
18
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