Xilinx LogiCORE IP AXI Product Manual page 20

Table 2-4: Top-Level Parameters (Cont'd)
Generic Parameter Name
C_S_AXI_CTL_
PROTOCOL
G41 C_NO_OF_LANES
G42 C_DEVICE_ID
G43 C_VENDOR_ID
G44 C_CLASS_CODE
G45 C_REV_ID
G46 C_SUBSYSTEM_ID
C_SUBSYSTEM_
G47
VENDOR_ID
C_PCIE_USE_MODE
C_PCIE_CAP_SLOT_
G48
IMPLEMENTED
G49 C_REF_CLK_FREQ
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
AXI4-Lite port
connection
definition to AXI AXI4LITE
Interconnect in the
Vivado IP integrator.
Core for PCIe Configuration Parameters
Number of PCIe
1, 2, 4, 8: 7 series FPGAs
Lanes
Device ID 16-bit vector
Vendor ID 16-bit vector
Class Code 24-bit vector
Rev ID 8-bit vector
Subsystem ID 16-bit vector
Subsystem Vendor
16-bit vector
ID
Specifies PCIe use
mode for underlying
See
serial transceiver
wrapper usage/ 1.0: For Kintex-7 325T IES
configuration (initial ES) silicon
(specific only to 7
1.1: For Virtex-7 485T IES
series).
(initial ES) silicon
This parameter
3.0: For GES (general ES)
ignored for
silicon
Zynq-7000 devices
(set to 3.0).
0: Not add-in card slot
1: Downstream port is
PCIE Capabilities
connected to add-in card
Register Slot
slot
Implemented
(valid only for Root
Complex)
0: 100 MHz
REFCLK input
1: 125 MHz
Frequency
2: 250 MHz - 7 series
FPGAs only
www.xilinx.com
Chapter 2: Product Specification
Allowable Values Default Value VHDL Type
0x00_0000
Table 2-6.
AXI4LITE String
1 Integer
std_logic_
0x0000
vector
std_logic_
0x0000
vector
std_logic_
vector
std_logic_
0x00
vector
std_logic_
0x0000
vector
std_logic_
0x0000
vector
1.0 String
0 Integer
0 Integer
20
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