Xilinx LogiCORE IP AXI Product Manual page 61

AXI DECERR Response
When the Master Bridge receives a DECERR response from the AXI bus, the request is
discarded and the Master DECERR (MDE) interrupt is asserted. If the request was
non-posted, a completion packet with the Completion Status = Unsupported Request (UR)
is returned on the bus for PCIe.
AXI SLVERR Response
When the Master Bridge receives a SLVERR response from the addressed AXI slave, the
request is discarded and the Master SLVERR (MSE) interrupt is asserted. If the request was
non-posted, a completion packet with the Completion Status = Completer Abort (CA) is
returned on the bus for PCIe.
Max Payload Size for PCIe, Max Read Request Size or 4K Page Violated
It is the responsibility of the requester to ensure that the outbound request adhere to the
Max Payload Size, Max Read Request Size, and 4 Kb Page Violation rules. If the master
bridge receives a request that violates one of these rules, the bridge processes the invalid
request as a valid request, which can return a completion that violates one of these
conditions or can result in the loss of data. The Master Bridge does not return a malformed
TLP completion to signal this violation.
Completion Packets
When the MAX_READ_REQUEST_SIZE is greater than the MAX_PAYLOAD_SIZE, a read
request for PCIe can ask for more data than the Master Bridge can insert into a single
completion packet. When this situation occurs, multiple completion packets are generated
up to MAX_PAYLOAD_SIZE, with the Read Completion Boundary (RCB) observed.
Poison Bit
When the poison bit is set in a transaction layer packet (TLP) header, the payload following
the header is corrupt. When the Master Bridge receives a memory request TLP with the
poison bit set, it discards the TLP and asserts the Master Error Poison (MEP) interrupt
strobe.
Zero Length Requests
When the Master Bridge receives a read request with the Length = 0x1, FirstBE = 0x00, and
LastBE = 0x00, it responds by sending a completion with Status = Successful Completion.
When the Master Bridge receives a write request with the Length = 0x1, FirstBE = 0x00, and
LastBE = 0x00 there is no effect.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
www.xilinx.com
Chapter 3: Designing with the Core
Send Feedback
61