Xilinx LogiCORE IP AXI Product Manual page 30

Table 2-12: Interrupt Decode Register
Bits Name
0 Link Down
1 ECRC Error
2 Streaming Error
3 Hot Reset
4 Reserved
Cfg Completion
7:5
Status
8 Cfg Timeout
9 Correctable
10 Non-Fatal
11 Fatal
15:12 Reserved
INTx Interrupt
16
Received
MSI Interrupt
17
Received
19:18 Reserved
Slave
20 Unsupported
Request
Slave Unexpected
21
Completion
Slave Completion
22
Timeout
23 Slave Error Poison
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
Indicates that Link-Up on the PCI Express link was lost. Not
RW1C 0
asserted unless link-up had previously been seen.
Indicates Received packet failed ECRC check.
RW1C 0
(Only applicable to Kintex-7 FPGA cores.)
Indicates a gap was encountered in a streamed packet on the TX
RW1C 0
interface (RW, RR, or CC).
RW1C 0 Indicates a Hot Reset was detected.
RO 0 Reserved
RW1C 0 Indicates config completion status.
Indicates timeout on an ECAM access.
RW1C 0
(Only applicable to Root Port cores.)
Indicates a correctable error message was received.
Requester ID of error message should be read from the Root Port
RW1C 0
FIFO.
(Only applicable to Root Port cores.)
Indicates a non-fatal error message was received.
Requester ID of error message should be read from the Root Port
RW1C 0
FIFO.
(Only applicable to Root Port cores.)
Indicates a fatal error message was received.
Requester ID of error message should be read from the Root Port
RW1C 0
FIFO.
(Only applicable to Root Port cores.)
RO 0 Reserved
Indicates an INTx interrupt was received.
Interrupt details should be read from the Root Port FIFO.
RW1C 0
(Only applicable to Root Port cores.)
Indicates an MSI(x) interrupt was received.
Interrupt details should be read from the Root Port FIFO.
RW1C 0
(Only applicable to Root Port cores.)
RO 0 Reserved
Indicates that a completion TLP was received with a status of
RW1C 0
0b001 - Unsupported Request.
Indicates that a completion TLP was received that was
RW1C 0
unexpected.
Indicates that the expected completion TLP(s) for a read request
RW1C 0 for PCIe was not returned within the time period selected by the
C_COMP_TIMEOUT parameter.
RW1C 0 Indicates the EP bit was set in a completion TLP.
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Chapter 2: Product Specification
Description
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