Xilinx LogiCORE IP AXI Product Manual page 28

VSEC Header Register (Offset 0x12C)
The VSEC Header register (described in
identifier for the layout and contents of the VSEC structure, as well as its revision and
length.
Table 2-9: VSEC Header Register
Bits Name
15:0 VSEC ID
19:16 VSEC REV
31:20 VSEC Length
Bridge Info Register (Offset 0x130)
The Bridge Info register (described in
information about the AXI4-Stream Bridge. Information in this register is static and does
not change during operation.
Table 2-10: Bridge Info Register
Bits Name
0 Gen2 Capable
1 Root Port Present
Up Config
2
Capable
15:3 Reserved
18:16 ECAM Size
31:19 Reserved
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Table
Core
Reset Value
Access
RO 0x0001
RO 0
RO 0x038
Table
Core Reset
Access Value
If set, indicates the link is Gen2 capable. Underlying integrated
RO 0
block and Link partner support PCIe Gen2 speed.
Indicates the underlying integrated block is a Root Port when
this bit is set.
RO 0
If set, Root Port registers are present in this interface.
Indicates the underlying integrated block is upconfig capable
RO
when this bit is set.
RO 0 Reserved
Size of Enhanced Configuration Access Mechanism (ECAM) Bus
Number field, in number of bits. If ECAM window is present,
value is between 1 and 8. If not present, value is 0. Total address
RO 0
bits dedicated to ECAM window is 20+(ECAM Size).
The size of the ECAM is determined by the parameter settings
of C_BASEADDR and C_HIGHADDR.
RO 0 Reserved
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Chapter 2: Product Specification
2-9) provides a unique (within a given vendor)
Description
ID value uniquely identifying the nature and format of
this VSEC structure.
Version of this capability structure. Hardcoded to 0h.
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hardcoded to
0x038 (56 decimal).
2-10) provides general configuration
Description
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