Xilinx LogiCORE IP AXI Product Manual page 38

Table 2-23: VSEC Header Register 2
Bits Name
15:0 VSEC ID
19:16 VSEC REV
31:20 VSEC Length
AXI Base Address Translation Configuration Registers (Offset
0x208 - 0x234)
The AXI Base Address Translation Configuration Registers and their offsets are shown in
Table 2-24 and the register bits are described in
in two configurations based on the top-level parameter C_AXIBAR_AS_n. When the BAR is
set to a 32-bit address space, then the translation vector should be placed into the
AXIBAR2PCIEBAR_nL register where n is the BAR number. When the BAR is set to a 64-bit
address space, then the most significant 32 bits are written into the AXIBAR2PCIEBAR_nU
and the least significant 32 bits are written into AXIBAR2PCIEBAR_nL. These registers are
only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 2-24: AXI Base Address Translation Configuration Registers
Offset
0x208
0x20C
0x210
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core
Reset Value
Access
RO 0x0002
RO 0x0
RO 0x038
Bits Register Mnemonic
AXIBAR2PCIEBAR_0U
31-0
31-0 AXIBAR2PCIEBAR_0L
31-0 AXIBAR2PCIEBAR_1U
31-0 AXIBAR2PCIEBAR_1L
AXIBAR2PCIEBAR_2U
31-0
31-0 AXIBAR2PCIEBAR_2L
31-0 AXIBAR2PCIEBAR_3U
AXIBAR2PCIEBAR_3L
31-0
31-0 AXIBAR2PCIEBAR_4U
31-0 AXIBAR2PCIEBAR_4L
31-0 AXIBAR2PCIEBAR_5U
AXIBAR2PCIEBAR_5L
31-0
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Chapter 2: Product Specification
Description
ID value uniquely identifying the nature and format of
this VSEC structure.
Version of this capability structure. Hardcoded to 0x0.
Length of the entire VSEC Capability structure, in bytes,
including the VSEC Capability register. Hardcoded to
0x038 (56 decimal).
Table 2-25. This set of registers can be used
38
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