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Table 2-3: Top-Level Interface Signals (Cont'd)
Signal Name
s_axi_awburst[1:0]
s_axi_awvalid
s_axi_awready
s_axi_wdata[c_s_axi_data_width-1:0]
s_axi_wstrb[c_s_axi_data_width/8-1:0]
s_axi_wlast
s_axi_wvalid
s_axi_wready
s_axi_bid[c_s_axi_id_width-1:0]
s_axi_bresp[1:0]
s_axi_bvalid
s_axi_bready
s_axi_arid[c_s_axi_id_width-1:0]
s_axi_araddr[c_s_axi_addr_width-1:0]
s_axi_arregion[3:0]
s_axi_arlen[7:0]
s_axi_arsize[2:0]
s_axi_arburst[1:0]
s_axi_arvalid
s_axi_arready
s_axi_rid[c_s_axi_id_width-1:0]
s_axi_rdata[c_s_axi_data_width-1:0]
s_axi_rresp[1:0]
s_axi_rlast
s_axi_rvalid
s_axi_rready
m_axi_awaddr[c_m_axi_addr_width-1:0]
m_axi_awlen[7:0]
m_axi_awsize[2:0]
m_axi_awburst[1:0]
m_axi_awprot[2:0]
m_axi_awvalid
m_axi_awready
m_axi_wdata[c_m_axi_data_width-1:0]
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
I/O Description
I
Slave write burst type
I
Slave address write valid
O
Slave address write ready
I
Slave write data
I
Slave write strobe
I
Slave write last
I
Slave write valid
O
Slave write ready
O
Slave response ID
O
Slave write response
O
Slave write response valid
I
Slave response ready
I
Slave read address ID
I
Slave read address
I
Slave read region decode
I
Slave read burst length
I
Slave read burst size
I
Slave read burst type
I
Slave read address valid
O
Slave read address ready
O
Slave read ID tag
O
Slave read data
O
Slave read response
O
Slave read last
O
Slave read valid
I
Slave read ready
AXI Master Interface
O
Master address write
O
Master write burst length
O
Master write burst size
O
Master write burst type
O
Master write protection type
O
Master write address valid
I
Master write address ready
O
Master write data
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Chapter 2: Product Specification
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