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Table 2-3: Top-Level Interface Signals (Cont'd)
Signal Name
m_axi_wstrb[c_m_axi_data_width/8-1:0]
m_axi_wlast
m_axi_wvalid
m_axi_wready
m_axi_bresp[1:0]
m_axi_bvalid
m_axi_bready
m_axi_araddr[c_m_axi_addr_width-1:0]
m_axi_arlen[7:0]
m_axi_arsize[2:0]
m_axi_arburst[1:0]
m_axi_arprot[2:0]
m_axi_arvalid
m_axi_arready
m_axi_rdata[c_m_axi_data_width-1:0]
m_axi_rresp[1:0]
m_axi_rlast
m_axi_rvalid
m_axi_rready
s_axi_ctl_awaddr[31:0]
s_axi_ctl_awvalid
s_axi_ctl_awready
s_axi_ctl_wdata[31:0]
s_ax_ctl_wstrb[3:0]
s_axi_ctl_wvalid
s_axi_ctl_wready
s_axi_ctl_bresp[1:0]
s_axi_ctl_bvalid
s_axi_ctl_bready
s_axi_ctl_araddr[31:0]
s_axi_ctl_arvalid
s_axi_ctl_arready
s_axi_ctl_rdata[31:0]
s_axi_ctl_rresp[1:0]
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
I/O Description
O
Master write strobe
O
Master write last
O
Master write valid
I
Master write ready
I
Master write response
I
Master write response valid
O
Master response ready
O
Master read address
O
Master read burst length
O
Master read burst size
O
Master read burst type
O
Master read protection type
O
Master read address valid
I
Master read address ready
I
Master read data
I
Master read response
I
Master read last
I
Master read valid
O
Master read ready
AXI4-Lite Control Interface
I
Slave write address
I
Slave write address valid
O
Slave write address ready
I
Slave write data
I
Slave write strobe
I
Slave write valid
O
Slave write ready
O
Slave write response
O
Slave write response valid
I
Slave response ready
I
Slave read address
I
Slave read address valid
O
Slave read address ready
O
Slave read data
O
Slave read response
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Chapter 2: Product Specification
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