Memory Map - Xilinx LogiCORE IP AXI Product Manual

Table 2-6: Silicon Version Specification
C_FAMILY C_PCIE_USE_MODE
1.1 = for Kintex-7 325T IES (initial silicon)
Kintex-7
3.0 = for GES (general silicon)
1.1 = for Virtex-7 485T IES (initial silicon)
Virtex-7
3.0 = for GES and Production (general silicon and Production silicon)
1.0 = for IES (initial silicon) as well as GES and Production (General silicon and Production
Artix-7
silicon) to use latest serial transceiver wrappers (only allowable value)
Zynq Not applicable. (set internally = 3.0)

Memory Map

The memory map shown in
Express core. These registers are described in more detail in the following section. All
registers are accessed through the AXI4-Lite Control Interface and are offset from
C_BASEADDR. During a reset, all registers return to default values.
Table 2-7: Register Memory Map
Accessibility Offset
RO - EP, R/W - RC 0x000 - 0x124
RO 0x128
RO 0x12C
RO 0x130
RO - EP, R/W - RC 0x134
R/W 0x138
R/W 0x13C
RO - EP, R/W - RC 0x140
RO 0x144
RO - EP, R/W - RC 0x148
RO - EP, R/W - RC 0x14C
RO - EP, R/W - RC 0x150
RO - EP, R/W - RC 0x154
RO - EP, R/W - RC 0x158
RO - EP, R/W - RC 0x15C
RO 0x160 - 0x1FF
RO 0x200
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Table 2-7 shows the address mapping for the AXI Bridge for PCI
Contents
PCIe Configuration Space Header
Vendor-Specific Enhanced Capability (VSEC)
Capability
VSEC Header
Bridge Info
Bridge Status and Control
Interrupt Decode
Interrupt Mask
Bus Location
Physical-Side Interface (PHY) Status/Control
Root Port Status/Control
Root Port MSI Base 1
Root Port MSI Base 2
Root Port Error FIFO Read
Root Port Interrupt FIFO Read 1
Root Port Interrupt FIFO Read 2
Reserved (zeros returned on read)
VSEC Capability 2
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Chapter 2: Product Specification
Location
Part of integrated PCIe
configuration space.
VSEC of integrated PCIe
configuration space.
AXI bridge defined
memory-mapped
register space.
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