Xilinx LogiCORE IP AXI Product Manual page 67

Component Name
Base name of the output f iles generated for the core. The name must begin with a letter
and can be composed of these characters: a to z, 0 to 9, and "_."
PCIe Device / Port Type
Indicates the PCI Express logical device type.
Reference Clock Frequency
Selects the frequency of the reference clock provided on sys_clk.
Slot Clock Configuration
Enables the Slot Clock Configuration bit in the Link Status register. Selecting this option
means the link is synchronously clocked. See
clocking options.
Silicon Type
Selects the silicon type.
PCIe Link Configuration
The PCIe Link Config page is shown in
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Clocking, page 42
Figure 4-2.
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