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Table 2-4: Top-Level Parameters (Cont'd)
Generic
Parameter Name
C_NUM_MSI_REQ
C_M_AXI_DATA_
G50
WIDTH
C_M_AXI_ADDR_
G51
WIDTH
G52
C_S_AXI_ID_WIDTH
C_S_AXI_DATA_
G53
WIDTH
C_S_AXI_ADDR_
G54
WIDTH
C_M_AXI_PROTOCOL
C_S_AXI_PROTOCOL
C_MAX_LINK_
G55
SPEED
G56
C_INTERRUPT_PIN
NUM_WRITE_
G57
OUTSTANDING
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
Specifies the size of
the MSI request
vector for selecting
0-5
the number of
requested message
values.
Memory Mapped AXI4 Parameters
AXI Master Bus Data
64: 7 series FPGAs only
width
128: 7 series FPGAs only
AXI Master Bus
32
Address width
AXI Slave Bus ID
4
width
AXI Slave Bus Data
64: 7 series FPGAs only
width
128: 7 series FPGAs only
AXI Slave Bus
32
Address width
Protocol definition
for M_AXI (Master
Bridge) port on AXI
AXI4
Interconnect in the
Vivado IP integrator.
Protocol definition
for S_AXI (Slave
Bridge) port on AXI
AXI4
Interconnect in the
Vivado IP integrator.
0: 2.5 GT/s - 7 series
Maximum PCIe link
speed supported
1: 5.0 GT/s - 7 series
0: No INTX support
(setting for Root Port)
Legacy INTX pin
1: INTA selected (only
support/select
allowable when core in
Endpoint configuration)
AXI4 Interconnect Parameters
1: Only one active AXI
AWADDR can be accepted
in the AXI slave bridge for
AXI Interconnect
PCIe
Slave Port Write
2: Maximum of two active
Pipeline Depth
AXI AWADDR values can
be stored in AXI slave
bridge for PCIe
www.xilinx.com
Chapter 2: Product Specification
Allowable Values
Default Value VHDL Type
0
Integer
64
Integer
32
Integer
4
Integer
64
Integer
32
Integer
AXI4
String
AXI4
String
0
Integer
0
Integer
2
Integer
21
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