Xilinx LogiCORE IP AXI Product Manual page 24

Table 2-5: Parameter Dependencies (Cont'd)
Generic Parameter
G21 C_AXIBAR_AS_3
G22 C_AXIBAR2PCIEBAR_3
G23 C_AXIBAR_4
G24 C_AXIBAR_HIGHADDR_4
G25 C_AXIBAR_AS_4
G26 C_AXIBAR2PCIEBAR_4
G27 C_AXIBAR_5
G28 C_AXIBAR_HIGHADDR_5
G29 C_AXIBAR_AS_5
G30 C_AXIBAR2PCIEBAR_5
G31 C_PCIEBAR_NUM
G32 C_PCIEBAR_AS
G33 C_PCIEBAR_LEN_0
G34 C_PCIEBAR2AXIBAR_0
G35 C_PCIEBAR_LEN_1
G36 C_PCIEBAR2AXIBAR_1
G37 C_PCIEBAR_LEN_2
G38 C_PCIEBAR2AXIBAR_2
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Affects Depends
G6
G4, G6
G24 G24
G23 G6, G23
G6
G4, G6
G28 G28
G27 G6, G27
G6
G4, G6
G33-G38
G34 G31
G31, G33
G36 G31
G31, G35
G38 G31
G31, G37
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Chapter 2: Product Specification
Description
Meaningful when G4 = 1.
G23 and G24 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G23 and G24 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
Meaningful if G4 = 1.
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
G27 and G28 define the range in
AXI-memory space that is responded
to by this device (AXIBAR)
Meaningful if G4 = 1.
If G31 = 1, then G32, G33 are
enabled.
If G31 = 2, then G32 - G36 are
enabled.
If G31 = 3, then G32 - G38 are
enabled
Only the high-order bits above the
length defined by G33 are
meaningful.
Only the high-order bits above the
length defined by G35 are
meaningful.
Only the high-order bits above the
length defined by G37 are
meaningful.
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