Xilinx LogiCORE IP AXI Product Manual page 17

Table 2-4: Top-Level Parameters (Cont'd)
Generic Parameter Name
G10 C_AXIBAR2PCIEBAR_0
G11 C_AXIBAR_1
C_AXIBAR_
G12
HIGHADDR_1
G13 C_AXIBAR_AS_1
G14 C_AXIBAR2PCIEBAR_1
G15 C_AXIBAR_2
C_AXIBAR_
G16
HIGHADDR_2
G17 C_AXIBAR_AS_2
G18 C_AXIBAR2PCIEBAR_2
G19 C_AXIBAR_3
C_AXIBAR_
G20
HIGHADDR_3
G21 C_AXIBAR_AS_3
G22 C_AXIBAR2PCIEBAR_3
G23 C_AXIBAR_4
C_AXIBAR_
G24
HIGHADDR_4
G25 C_AXIBAR_AS_4
G26 C_AXIBAR2PCIEBAR_4
G27 C_AXIBAR_5
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Description
PCIe BAR to which
AXI BAR_0 is Valid address for PCIe
mapped
AXI BAR_1 aperture
Valid AXI address
low address
AXI BAR_1 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_1 address
size
1: 64 bit
PCIe BAR to which
AXI BAR_1 is Valid address for PCIe
mapped
AXI BAR_2 aperture
Valid AXI address
low address
AXI BAR_2 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_2 address
size
1: 64 bit
PCIe BAR to which
AXI BAR_2 is Valid address for PCIe
mapped
AXI BAR_3 aperture
Valid AXI address
low address
AXI BAR_3 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_3 address
size
1: 64 bit
PCIe BAR to which
AXI BAR_3 is Valid address for PCIe
mapped
AXI BAR_4 aperture
Valid AXI address
low address
AXI BAR_4 aperture
Valid AXI address
high address
0: 32 bit
AXI BAR_4 address
size
1: 64 bit
PCIe BAR to which
AXI BAR_4 is Valid address for PCIe
mapped
AXI BAR_5 aperture
Valid AXI address
low address
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Chapter 2: Product Specification
Allowable Values Default Value VHDL Type
(2)
0xFFFF_FFFF
(1)(3)(4)
0xFFFF_FFFF
(1)(3)(4)
0x0000_0000
(2)
0xFFFF_FFFF
(1)(3)(4)
0xFFFF_FFFF
(1)(3)(4)
0x0000_0000
(2)
0xFFFF_FFFF
(1)(3)(4)
0xFFFF_FFFF
(1)(3)(4)
0x0000_0000
(2)
0xFFFF_FFFF
(1)(3)(4)
0xFFFF_FFFF
(1)(3)(4)
0x0000_0000
(2)
0xFFFF_FFFF
(1)(3)(4)
0xFFFF_FFFF
std_logic_
vector
std_logic_
vector
std_logic_
vector
0 Integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
0 Integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
0 Integer
std_logic_
vector
std_logic_
vector
std_logic_
vector
0 Integer
std_logic_
vector
std_logic_
vector
17
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