Xilinx LogiCORE IP AXI Product Manual page 68

X-Ref Target - Figure 4-2
Number of Lanes
The AXI Bridge for PCI Express® core requires the selection of the initial lane width.
Table 4-1 defines the available widths and associated generated core. Wider lane width
cores can train down to smaller lane widths if attached to a smaller lane-width device.
Table 4-1: Lane Width and Product Generated
Lane Width
x1
x2
x4
x8
Link Speed
The AXI Bridge for PCI Express core allows the selection of Maximum Link Speed supported
by the device. Table 4-2
Higher link speed cores are capable of training to a lower link speed if connected to a lower
link speed capable device.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 4-2: PCIe Link Configuration
Product Generated
1-Lane
2-Lane
4-Lane
8-Lane
defines the lane widths and link speeds supported by the device.
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