Xilinx LogiCORE IP AXI Product Manual page 75

Aperture High Address
Sets the upper address threshold for the address range associated to the BAR. You should
edit this parameter to fit design requirements.
AXI to PCIe Translation
Configures the translation mapping between AXI and PCI Express address space. You
should edit this parameter to fit design requirements.
SRIOV BARs can be one of two sizes:
• 32-bit BARs: The address space can be as small as 16 bytes or as large as 2 gigabytes.
Used for Memory to I/O.
• 64-bit BARs: The address space can be as small as 128 bytes or as large as 8 exabytes.
Used for Memory only.
AXI System
The AXI System screen shown in
parameters.
X-Ref Target - Figure 4-7
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 4-7 sets the AXI Addressing and AXI Interconnect
Figure 4-7: AXI System Settings
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Chapter 4: Design Flow Steps
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