Xilinx LogiCORE IP AXI Product Manual page 33

PHY Status/Control Register (Offset 0x144)
The PHY Status/Control register (described in
PHY state, as well as control of speed and rate switching for Gen2-capable cores.
Table 2-15: PHY Status/Control Register
Bits Name
0 Link Rate
2:1 Link Width
8:3 LTSSM State
10:9 Lane Reversal
11 Link Up
15:12 Reserved
Directed Link
17:16
Width
Directed Link
18
Speed
Directed Link
19
Autonomous
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
RO 0 Reports the current link rate. 0b = 2.5 GT/s, 1b = 5.0 GT/s.
Reports the current link width. 00b = x1, 01b = x2, 10b = x4, 11b
RO 0
= x8.
Reports the current Link Training and Status State Machine
RO 0 (LTSSM) state. Encoding is specific to the underlying integrated
block.
Reports the current lane reversal mode.
• 00b: No reversal
RO 0 • 01b: Lanes 1:0 reversed
• 10b: Lanes 3:0 reversed
• 11b: Lanes 7:0 reversed
Reports the current PHY Link-up state.
• 1b: Link up
• 0b: Link down
RO 0
Link up indicates the core has achieved link up status, meaning
the LTSSM is in the L0 state and the core can send/receive data
packets.
RO 0 Reserved
Specifies completer link width for a directed link change
operation. Only acted on when Directed Link Change specifies a
width change.
• 00b: x1
RW 0
• 01b: x2
• 10b: x4
• 11b: x8
Specifies completer link speed for a directed link change
operation. Only acted on when Directed Link Change specifies a
speed change.
RW 0
• 0b: 2.5 GT/s
• 1b: 5.0 GT/s
Specifies link reliability or autonomous for directed link change
operation.
RW 0
• 0b: Link reliability
• 1b: Autonomous
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Chapter 2: Product Specification
Table 2-15) provides the status of the current
Description
33
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