Malformed Tlp; Abnormal Conditions - Xilinx LogiCORE IP AXI Product Manual

Table 3-5: MSI Vectors Enabled in Message Control Register (Cont'd)
Value
110
111
Additional IP is required in the Endpoint PCIe system to create the prioritization scheme for
the MSI vectors on the PCIe interface.
Legacy Interrupts
The bridge supports legacy interrupts for PCI if selected by the C_INTERRUPT_PIN
parameter. (Can only be set to 1 when C_INCLUDE_RC = 0.) A value of 1 selects INTA, as
defined in Table
output pin indicates that the bridge has endpoint MSI functionality disabled
(MSI_enable = '0'), the intx_msi_request pin is defined as intx. When the intx pin
goes High, an assert INTA message is sent. When the INTX pin goes Low, a deassert INTA
message is sent. These messages are defined in the PCI 2.1 specification. The
intx_msi_request pin input is valid only when the bridge is operating in Endpoint mode
(C_INCLUDE_RC=0).

Malformed TLP

The integrated block for PCI Express detects a malformed TLP. For the IP configured as an
Endpoint core, a malformed TLP results in a fatal error message being sent upstream if error
reporting is enabled in the Device Control Register.
For the IP configured as a Root Port, when a malformed TLP is received from the Endpoint,
this can fall under one of several types of violations as per the PCIe specification. For
example, if a Received TLP has the Error Poison bit set, this is discarded by the MM/S master
bridge, and the MEP (Master Error Poison) bit is set in the Interrupt Decode register.

Abnormal Conditions

This section describes how the Slave side
Bridge for PCI Express core handle abnormal conditions.
Slave Bridge Abnormal Conditions
Slave Bridge abnormal conditions are classified as: Illegal Burst Type and Completion TLP
Errors. The following sections describe the manner in which the Bridge handles these errors.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Number of Messages Requested
Reserved
Reserved
2-4. If a legacy interrupt for PCI support is selected and the msi_enable
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Chapter 3: Designing with the Core
Output Signal, MSI_Vector_Width (2:0)
(Table 3-6) and Master side
N/A
N/A
(Table 3-7) of the AXI
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