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unique. The default value, 10EEh, is the Vendor ID for Xilinx. Enter your vendor
identification number here. FFFFh is reserved.
•
Device ID: A unique identifier for the application; the default value, which depends on
the configuration selected, is 70<link speed><link width>h. This field can be any value;
change this value for the application.
•
Revision ID: Indicates the revision of the device or application; an extension of the
Device ID. The default value is 00h; enter values appropriate for the application.
•
Subsystem Vendor ID: Further qualifies the manufacturer of the device or application.
Enter a Subsystem Vendor ID here; the default value is 10EEh. Typically, this value is the
same as Vendor ID. Setting the value to 0000h can cause compliance testing issues.
•
Subsystem ID: Further qualifies the manufacturer of the device or application. This
value is typically the same as the Device ID; the default value depends on the lane
width and link speed selected. Setting the value to 0000h can cause compliance testing
issues.
Class Code
The Class Code identifies the general function of a device, and is divided into three
byte-size fields. The Vivado IDE allows you to either enter the 24-bit value manually
(default) by either selecting the Enter Class Code Manually checkbox or using the Class
Code lookup assistant to populate the field. De-select the checkbox to enable the Class
Code assistant.
•
Base Class: Broadly identifies the type of function performed by the device.
•
Sub-Class: More specifically identifies the device function.
•
Interface: Defines a specific register-level programming interface, if any, allowing
device-independent software to interface with the device.
Class code encoding can be found in the PCI-SIG® specifications
Class Code Look-up Assistant
The Class Code Look-up Assistant provides the Base Class, Sub-Class and Interface values
for a selected general function of a device. This Look-up Assistant tool only displays the
three values for a selected function. You must enter the values in Class Code for these
values to be translated into device settings.
Base Address Registers
The Base Address Registers (BARs) screens shown in
space for the Endpoint configuration. Each BAR (0 through 5) configures the BAR Aperture
Size and Control attributes of the Physical Function, as described in
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 4-4
www.xilinx.com
Chapter 4: Design Flow Steps
[Ref
5].
set the base address register
Table 4-3, page
72.
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