Xilinx LogiCORE IP AXI Product Manual page 37

Root Port Interrupt FIFO Read Register 2 (Offset 0x15C)
Reads from this location return queued interrupt messages. Data from each read follows the
format shown in
register, while the header information is presented in the Root Port Interrupt FIFO Read 1
register. The interrupt-handling flow should be to read the Root Port Interrupt FIFO Read 1
register first, immediately followed by this register. For non-Root Port cores, reads return 0.
For INTx interrupts, reads return zero.
Reads are non-destructive. Removing the message from the FIFO requires a write to either
Note:
this register or the Root Port Interrupt FIFO Read 1 register (write value is ignored).
Table 2-21: Root Port Interrupt FIFO Read Register 2
Bits Name
15:0 Message Data
31:16 Reserved
VSEC Capability Register 2 (Offset 0x200)
The VSEC capability register (described in
to appear as though it is a part of the underlying integrated block PCIe configuration space.
The VSEC is inserted immediately following the last enhanced capability structure in the
underlying block. VSEC is defined in §7.18 of the PCI Express Base Specification, v1.1 (§7.19
of v2.0) [Ref 5].
This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
Table 2-22: VSEC Capability Register 2
Bits Name
15:0 VSEC Capability ID
19:16 Capability Version
Next Capability
31:20
Offset
VSEC Header Register 2 (Offset 0x204)
The VSEC Header Register 2 (described in
vendor) identifier for the layout and contents of the VSEC structure, as well as its revision
and length.
This register is only included if C_INCLUDE_BAR_OFFSET_REG = 1.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Table 2-21. For MSI interrupts, the message payload is presented in this
Core Reset
Access Value
RWC 0 Payload for MSI messages.
RO 0 Reserved
Core Reset
Access Value
PCI-SIG defined ID identifying this Enhanced Capability as a
RO 0x000B
Vendor-Specific capability. Hardcoded to 0x000B.
RO 0x1 Version of this capability structure. Hardcoded to 0x1.
RO 0x000 Offset to next capability.
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Chapter 2: Product Specification
Description
Table 2-22) allows the memory space for the core
Description
Table 2-23) provides a unique (within a given
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