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X-Ref Target - Figure 5-1
The example design supports Verilog as the target language.
Note:
Customizing and Generating the Example Design
In Customize IP dialog box, make the following selections for the example design.
1. In the PCIE:Basics page, the example design supports only an Endpoint (EP) device.
2. The PCIE:ID defaults are supported.
3. The PCIE:BARS defaults are supported.
4. The PCIE:Misc page defaults are supported.
5. In the AXI:BARS page, default values are assigned to the Base Address, High Address,
and AXI to PCIe Translation values.
6. The AXI:System page default values are supported:
After customizing the core, right-click the component name, and select Open IP Example
Note:
Design. This opens a separate example design. Simulate the core by following the steps in the next
section.
Simulating the Example Design
The example design can be run in any configuration using:
•
Vivado Simulator
•
Cadence IES Simulator
•
Mentor Graphics Questa® SIM
•
VCS Simulator
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Figure 5-1: Example Design Block Diagram
www.xilinx.com
Chapter 5: Example Design
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