Xilinx LogiCORE IP AXI Product Manual page 76

BASEADDR
Sets the AXI Base Address for the device. You should edit this parameter to fit design
requirements.
HIGHADDR
Sets the AXI High Address threshold for the device. You should edit this parameter to fit
design requirements.
S AXI ID WIDTH
Sets the ID width for the AXI Slave Interface.
Multiple IDs are not supported for AXI Master Interface. Therefore, all signals concerned with
Note:
ID are not available at AXI Master Interface.
S AXI ADDR WIDTH
AXI supports 32-bit addressing so this field is always set to 32.
S AXI DATA WIDTH
Sets the data bus width for the AXI Slave interface. This can be 64-bit or 128-bit based on
your requirements. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum
performance.
M AXI ADDR WIDTH
AXI supports 32-bit addressing so this field is always set to 32.
M AXI DATA WIDTH
Sets the data bus width for the AXI Master interface. This can be 64-bit or 128-bit based on
your requirement. For X4G2 and X8G1, the core supports only 128-bit to achieve maximum
performance.
S AXI SUPPORTS NARROW BURST
Configures the IP to accept narrow burst transactions. When not enabled, the IP is
optimized accordingly.
Shared Logic
Enables you to share common blocks across multiple instantiations by selecting one or
more of the options on this page. For a details description of the shared logic feature, see
Shared Logic in Chapter
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
3.
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Chapter 4: Design Flow Steps
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