Xilinx LogiCORE IP Manuals

Manuals and User Guides for Xilinx LogiCORE IP. We have 3 Xilinx LogiCORE IP manuals available for free PDF download: Product Manual, User Manual

Xilinx LogiCORE IP Product Manual

Xilinx LogiCORE IP Product Manual (142 pages)

Brand: Xilinx | Category: Controller | Size: 2.27 MB

Table of Contents

Table of Contents
2
Send Feedback
4
IP Facts
5
Chapter 1: Overview

6
- Additional Features
  8
- About the Core
  8
- Recommended Design Experience
  8
- Applications
  9
- Licensing and Ordering Information
  10
- Feedback
  11
Chapter 2: Product Specification

12
- Standards Compliance
  12
- Performance
  12
- Resource Utilization
  13
- Verification
  15
- Port Descriptions
  16
- Register Space
  34
Chapter 3 : Designing with the Core

70
Chapter 4 : Core Architecture

72
- System Overview
  72
- Functional Description
  74
Chapter 5 : Interfacing to the Core

76
Chapter 6 : Design Considerations

90
Chapter 7 : Design Flow Steps

105
- Customizing and Generating the Core
  105
- Output Generation
  109
- Simulation
  111
Chapter 8: Detailed Example Design

115
- Chapter 8: Detailed Example Design
  116
Chapter 9: Test Bench

118
Appendix A: Verification and Interoperability

119
- Simulation
  119
Appendix B: Migrating and Upgrading

120
- Device Migration
  120
Appendix C:debugging Designs

126
- Finding Help on Xilinx.com
  126
- Technical Support
  127
- Debug Tools
  128
- Hardware Debug
  130
Appendix D: Additional Resources and Legal Notices

140
- Xilinx Resources
  140
- Additional Core Resources
  141
- Please Read: Important Legal Notices
  142

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Xilinx LogiCORE IP User Manual

Xilinx LogiCORE IP User Manual (102 pages)

Xilinx LogiCORE IP Video Scaler v4.0 User Guide

Brand: Xilinx | Category: Media Converter | Size: 3.16 MB

Table of Contents

Revision History
2
Table of Contents
3
Schedule of Figures
7
Schedule of Tables
9
Preface: about this Guide
11
- Guide Contents
  11
- Additional Resources
  12
- Conventions
  12
  - Typographical
    12
  - Online Document
    13
Chapter 1: Introduction

15
- About the Core
  15
- Recommended Experience
  15
- Additional Core Resources
  15
  - Documentation
    15
  - Technical Support
    15
- Providing Feedback
  16
  - Core
    16
  - Documentation
    16
- Nomenclature
  16
Chapter 2: Overview

19
Chapter 3: Implementation

21
- Basic Architecture
  21
- I/O Buffering, Clock Domains
  22
Chapter 4 : Video I/O Interface and Timing

23
- Data Source: Live Video
  23
  - Input Data and Timing Signals
    23
    
    General Input Handshaking Principles
    23
    
    Hblank_In Input
    25
    
    Active_Video_In Input
    26
- Data Source: Memory
  27
- Output Data and Timing Signals
  28
Chapter 5: Scaler Architectures

29
- Architecture Descriptions
  29
- GUI Operation
  31
Chapter 6: Control Interface

33
Chapter 7 : Scaler Aperture

39
- Input Aperture Definition
  39
- Cropping
  40
Chapter 8: Coefficients

41
Chapter 9: Performance

61
- Live Video Mode
  62
- Memory Mode
  67
Appendix A: Use Cases

71
- Typical Uses
  71
Appendix B: Programmer Guide

75
- Introduction
  75
- Conventions
  75
- Register Definitions
  75
  - Filter Coefficient Calculations
    85
- Video Scaler Flow Diagram
  86
- System Timing Diagram
  87
- Proposed API Function Calls
  88
  - L0 API Function Calls
    88
  - L1 API Function Calls
    89
  - L2 API Function Calls
    89
- Example Settings
  90
  - Pass Thru
    90
  - Down Sample by 2 in Horizontal and Vertical
    91
Appendix C: System Level Design

93
- Introduction
  93
- Example System General Configuration
  93
- Control Buses
  94
- VDMA0 Configuration
  94
- VDMA1 Configuration
  95
- VDMA2 Configuration
  95
- Video Scaler Configuration
  95
- MPMC Configuration
  95
  - Scaler READ-Port
    95
  - Scaler WRITE-Port
    96
- Cropping from Memory
  96
- OSD Configuration
  96
- EDK MHS File Text
  96

Xilinx LogiCORE IP Product Manual

Xilinx LogiCORE IP Product Manual (50 pages)

SMPTE2022-5/6 Video over IP Receiver v2.1

Brand: Xilinx | Category: Receiver | Size: 1.48 MB

Table of Contents

Table of Contents
2
Section I: Summary

5
- Chapter 1: Overview
  
  7
- Chapter 2: Product Specification
  
  9
  - Standards
    9
  - Performance
    9
  - Resource Utilization
    10
  - Port Descriptions
    15
  - Register Space
    22
- Chapter 3: Designing with the Core
  
  27
  - Clocking
    28
    
    Resets
    28
    
    Memory Requirement
    28
Section II: Vivado Design Suite

29
- Chapter 4: Customizing and Generating the Core
  
  30
  - Gui
    30
  - Output Generation
    31
- Chapter 5: Constraining the Core
  
  32
  - Required Constraints
    32
    
    Device, Package, and Speed Grade Selections
    32
    
    Clock Frequencies
    32
    
    Clock Management
    32
    
    Clock Placement
    33
    
    Banking
    33
    
    Transceiver Placement
    33
    
    I/O Standard and Placement
    33
Section III: Ise Design Suite

34
- Chapter 6: Customizing and Generating the Core
  
  35
  - Gui
    35
  - Parameter Values in the XCO File
    36
  - Output Generation
    37
- Chapter 7: Constraining the Core
  
  38
  - Required Constraints
    38
    
    Device, Package, and Speed Grade Selections
    38
    
    Clock Frequencies
    38
    
    Clock Management
    38
    
    Clock Placement
    39
    
    Banking
    39
    
    Transceiver Placement
    39
    
    I/O Standard and Placement
    39
- Chapter 8: Detailed Example Design
  
  40
Section IV: Appendices

41
- Appendix A: Verification, Compliance, and Interoperability
  
  42
  - Hardware Testing
    42
- Appendix B: Migrating
  
  43
- Appendix C: Debugging
  
  44
  - Finding Help on Xilinx.com
    44
  - Interface Debug
    46
- Appendix D: Additional Resources
  
  48
  - Xilinx Resources
    48
    
    References
    48
    
    Technical Support
    49
    
    Revision History
    49
    
    Notice of Disclaimer
    50

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