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Table 3-3: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs (Cont'd)
AXI4 Memory-Mapped Transaction
INCR Burst Read of 32-bit address AXIBAR
INCR Burst Write to 32-bit address AXIBAR
Table 3-4: AXI4-Stream PCIe TLPs to AXI4 Memory Mapped Transactions
AXI4-Stream PCIe TLPs
MemRd 32 (3DW) of PCIEBAR
MemWr 32 (3DW) to PCIEBAR
MemRd 64 (4DW) of PCIEBAR
MemWr 64 (4DW) to PCIEBAR
Transaction Ordering for PCIe
The AXI Bridge for PCI Express core conforms to strict PCIe transaction ordering rules. See
the PCIe v2.1 Specification
implemented in the AXI Bridge for PCI Express core to enforce the PCIe transaction ordering
rules on the highly-parallel AXI bus of the bridge. The rules are enforced without regard to
the Relaxed Ordering attribute bit within the TLP header:
•
The bresp to the remote (requesting) AXI4 master device for a write to a remote PCIe
device is not issued until the MemWr TLP transmission is guaranteed to be sent on the
PCIe link before any subsequent TX-transfers.
•
A remote AXI master read of a remote PCIe device is not permitted to pass any previous
or simultaneous AXI master writes to a remote PCIe device that occurs previously or at
the same time. Timing is based off the AXI arvalid signal timing relative to the AXI
awvalid. Any AXI write transaction in which awvalid was asserted before or at the
same time as the arvalid for a read from pcie is asserted causes the MemRd TLP(s) to
be held until the pipelined or simultaneous MemWr TLP(s) have been sent.
•
A remote PCIe device read of a remote AXI slave is not permitted to pass any previous
remote PCIe device writes to a remote AXI slave received by the AXI Bridge for PCI
Express core. The AXI read address phase is held until the previous AXI write
transactions have completed and bresp has been received for the AXI write
transactions.
•
Read completion data received from a remote PCIe device are not permitted to pass
any remote PCIe device writes to a remote AXI slave received by the AXI Bridge for PCI
Express core prior to the read completion data. The bresp for the AXI write(s) must be
received before the completion data is presented on the AXI read data channel.
•
Read data from a remote AXI slave is not permitted to pass any remote AXI master
writes to a remote PCIe device initiated on the AXI bus prior to or simultaneously with
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
AXI4-Stream PCIe TLPs
MemRd 64 (4DW)
MemWr 64 (4DW)
AXI4 Memory-Mapped Transaction
INCR Burst Read with 32-bit address
INCR Burst Write with 32-bit address
INCR Burst Read with 32-bit address
INCR Burst Write with 32-bit address
[Ref 5]
for the complete rule set. The following behaviors are
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