Shared Logic - Xilinx LogiCORE IP AXI Product Manual

Shared Logic

This new feature allows you to share common blocks across multiple instantiations. It
minimizes the amount of required HDL modifications. You can use your own system-level
clocking or reset circuit. You can modify some of these blocks due to system requirements
(for example, swapping a BUFG for a BUFH). You can instantiate multiple cores and share
'common/shared logic' from one core among all instantiated cores. This is only applicable
for Endpoint mode, and not Root Port mode.
In the Vivado Design Suite, the shared logic options are available in the Shared Logic page
when customizing the core.
There are four types of logic sharing:
• Shared Clocking
• Shared GT_COMMON
• Shared GT_COMMON and Clocking
• Internal Shared GT_COMMON and Clocking
Shared Clocking
To use the share clocking feature, select Include Shared Logic (Clocking) in example
design option in the in the Shared Logic tab
When this feature is selected, the mixed-mode clock manager (MMCM) instance is removed
from the pipe wrappers and is moved into the support wrapper of the example design. It
also brings out additional ports to the top level to enable sharing of the clocks.
You also have the option to modify and use the unused outputs of the MMCM.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
(Figure 3-3).
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Chapter 3: Designing with the Core
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