Xilinx LogiCORE IP AXI Product Manual page 32

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Table 2-13: Interrupt Mask Register (Cont'd)
Bits
Name
INTx Interrupt
16
Received
MSI Interrupt
17
Received
19:18
Reserved
Slave
20
Unsupported
Request
Slave Unexpected
21
Completion
Slave Completion
22
Timeout
23
Slave Error Poison
Slave Completer
24
Abort
25
Slave Illegal Burst
26
Master DECERR
27
Master SLVERR
Master Error
28
Poison
31:29
Reserved
Bus Location Register (Offset 0x140)
The Bus Location register reports the Bus, Device, and Function number, and the Port
number for the PCIe port
Table 2-14: Bus Location Register
Bits
Name
2:0
Function Number
7:3
Device Number
15:8
Bus Number
23:16
Port Number
31:24
Reserved
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core
Reset
Access
Value
Enables interrupts for INTx Interrupt events when bit is set.
RO
0
(Only writable for Root Port Configurations, otherwise =0)
Enables interrupts for MSI Interrupt events when bit is set.
RO
0
(Only writable for Root Port Configurations, otherwise =0)
RO
0
Reserved
Enables the Slave Unsupported Request interrupt when bit is
RW
0
set.
Enables the Slave Unexpected Completion interrupt when bit is
RW
0
set.
RW
0
Enables the Slave Completion Timeout interrupt when bit is set.
RW
0
Enables the Slave Error Poison interrupt when bit is set.
RW
0
Enables the Slave Completer Abort interrupt when bit is set.
RW
0
Enables the Slave Illegal Burst interrupt when bit is set.
RW
0
Enables the Master DECERR interrupt when bit is set.
RW
0
Enables the Master SLVERR interrupt when bit is set.
RW
0
Enables the Master Error Poison interrupt when bit is set.
RO
0
Reserved
(Table
2-14).
Core
Reset
Access
Value
RO
0
Function number of the port for PCIe. Hard-wired to 0.
Device number of port for PCIe. For Endpoint, this register is RO
RO
0
and is set by the Root Port.
Bus number of port for PCIe. For Endpoint, this register is RO and
RO
0
is set by the external Root Port.
RW
0
Sets the Port number field of the Link Capabilities register.
RO
0
Reserved
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Chapter 2: Product Specification
Description
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