Ip Facts - Xilinx LogiCORE IP AXI Product Manual

Introduction
The Xilinx LogiCORE™ IP AXI Root Port/
®
Endpoint (RP/EP) Bridge for PCI Express® core
is an interface between the AXI4 and PCI
Express. Definitions and references are
provided in this document for all of the
functional modules, registers, and interfaces
that are implemented in the AXI Bridge for PCI
Express core. Definitions are also provided for
the hardware implementation and software
interfaces to the AXI Bridge for PCI Express core
in supported FPGA devices.
Features
• Zynq®-7000, Kintex®-7, Virtex®-7, and
Artix®-7 FPGA Integrated Blocks for PCI
Express
• Maximum Payload Size (MPS) up to 256 bytes
• Multiple Vector Messaged Signaled Interrupts
(MSIs)
• Legacy interrupt support
• Memory-mapped AXI4 access to PCIe® space
• PCIe access to memory-mapped AXI4 space
• Tracks and manages Transaction Layer Packets
(TLPs) completion processing
• Detects and indicates error conditions with
interrupts
• Optimal AXI4 pipeline support for enhanced
performance
• Compliant with Advanced RISC Machine
(ARM®) Advanced Microcontroller Bus
Architecture 4 (AMBA®) AXI4 specification
• Supports up to three PCIe 32-bit or 64-bit
PCIe Base Address Registers (BARs) as
Endpoint
• Supports a single PCIe 32-bit or 64-bit BAR as
Root Port
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Supported
Device
(1)
Family
Supported
User Interfaces
Resources
Design Files
Example
Design
Test Bench
Constraints
File
Simulation
Model
Supported
(2)
S/W Driver
Design Entry
Simulation
Synthesis
Provided by Xilinx @
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog. See also
2. Standalone driver details can be found in the SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux
OS and driver support information is available from
wiki.xilinx.com.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes
4. Except for XC7VX485T, Virtex 7 devices are not supported.
www.xilinx.com
LogiCORE IP Facts Table
Core Specifics
Zynq-7000, 7 Series
Provided with Core
Standalone and Linux
(3)
Tested Design Flows
Vivado® Design Suite
Vivado IP integrator
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
Support
www.xilinx.com/support
Table 2-1, page 11.
Guide.
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Product Specification

IP Facts

(1)
AXI4
See Table 2-2
VHDL and Verilog
Verilog
Verilog
XDC
Not Provided
Vivado Synthesis
4