Xilinx LogiCORE IP AXI Product Manual page 29

Bridge Status and Control Register (Offset 0x134)
The Bridge Status and Control register (described in
the current state of the AXI4-Stream Bridge. It also provides control over how reads and
writes to the Core Configuration Access aperture are handled.
Table 2-11: Bridge Status and Control Register
Bits Name
0 ECAM Busy
7:1 Reserved
Global
8
Disable
15:9 Reserved
16 RW1C as RW
17 RO as RW
31:18 Reserved
Interrupt Decode Register (Offset 0x138)
The Interrupt Decode register (described in
host processor interrupt service routine can determine what is causing the interrupt to be
asserted and how to clear the interrupt. Writing a 1'b1 to any bit of the Interrupt Decode
register clears that bit except for the Correctable, Non-Fatal, and Fatal bits.
Follow this sequence to clear the Correctable, Non-Fatal, and Fatal bits:
1. Clear the Root Port Error FIFO (0x154) by performing first a read, followed by write-back
of the same register.
2. Write to the Interrupt Decode Register (0x138) with '1' to the appropriate error bit to
clear it.
An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert
IMPORTANT:
unless the corresponding bit in the Interrupt Mask register is also set.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
Indicates an ECAM access is in progress (waiting for
RO 0
completion).
RO 0 Reserved
When set, disables interrupt line from being asserted. Does not
RW 0
prevent bits in Interrupt Decode register from being set.
RO 0 Reserved
When set, allows writing to core registers which are normally
RW 0
RW1C.
When set, allows writing to certain registers which are normally
RW 0 RO.
(Only supported for Kintex-7 FPGA cores.)
RO 0 Reserved
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Chapter 2: Product Specification
Table 2-11) provides information about
Description
Table 2-12) provides a single location where the
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