Constraining The Core - Xilinx LogiCORE IP AXI Product Manual

Output Generation
For details, see "Generating IP Output Products" in the Vivado Design Suite User Guide:
Designing with IP (UG896)
For information regarding the example design, see
Chapter 5.

Constraining the Core

Required Constraints
The AXI Bridge for PCI Express® core requires a clock period constraint for the REFCLK
input that agrees with the C_REF_CLK_FREQ parameter setting. In addition, pin-placement
(LOC) constraints are needed that are board/part/package specific.
See Placement Constraints
Additional information on clocking can be found in the Xilinx Solution Center for PCI
Express (see Solution Centers, page
System Integration
A typical embedded system including the AXI Bridge for PCI Express core is shown in
Figure 2-2, page
can include the need to connect the MicroBlaze™ processor or Zynq® device ARM®
processor peripheral to communicate with PCI Express™ (in addition to the AXI4-Lite
register port on the PCIe bridge). A helper core is available to achieve this functionality and
bridges transactions from the AXI4-Lite MicroBlaze processor peripheral ports (DP and IP)
to the AXI4 Interconnect (connected to the AXI Bridge for PCI Express). The
axi2axi_connector IP core
The AXI Bridge for PCI Express core can be configured with each port connection for an AXI
Vivado IP integrator system topology. When instantiating the core, ensure the following bus
interface tags are defined.
BUS_INTERFACE M_AXI
BUS_INTERFACE S_AXI
BUS_INTERFACE S_AXI_CTL
PCIe Clock Integration
The PCIe differential clock input in the system might need to use a differential input buffer
(that is instantiated separately) from the AXI Bridge for the PCIe core. The Vivado IP
integrator automatically inserts the appropriate clock buffer.
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
[Ref 9].
for more details on the constraint paths for FPGA architectures.
88).
10. Some additional components to this system in the Vivado IP integrator
[Ref 6] provides this support.
www.xilinx.com
Chapter 4: Design Flow Steps
Example Design Output Structure in
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