Xilinx LogiCORE IP AXI Product Manual page 34

Table 2-15: PHY Status/Control Register (Cont'd)
Bits Name
Directed Link
21:20
Change
31:22 Reserved
Root Port Status/Control Register (Offset 0x148)
The Root Port Status/Control register provides access to Root Port specific status and
control. This register is only implemented for Root Port cores. For non-Root Port cores,
reads return 0 and writes are ignored (described in
Table 2-16: Root Port Status/Control Register
Bits Name
0 Bridge Enable
15:1 Reserved
Error FIFO Not
16
Empty
Error FIFO
17
Overflow
Interrupt FIFO Not
18
Empty
Interrupt FIFO
19
Overflow
Completion
27:20
Timeout
31:28 Reserved
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Core Reset
Access Value
Directs LTSSM to initiate a link width and/or speed change.
• 00b: No change
RW 0 • 01b: Force link width
• 10b: Force link speed
• 11b: Force link width and speed
RO 0 Reserved
Core Reset
Access Value
When set, allows the reads and writes to the AXIBARs to be
presented on the PCIe bus. Root Port software needs to write 1
RW 0 to this bit when enumeration is done. AXI Enhanced PCIe Bridge
clears this location when link up to link down transition occurs.
Default is set to 0.
RO 0 Reserved.
RO 0 Indicates that the Root Port Error FIFO has data to read.
Indicates that the Root Port Error FIFO overflowed and an error
RW1C 0
message was dropped. Writing a 1 clears the overflow status.
RO 0 Indicates that the Root Port Interrupt FIFO has data to read.
Indicates that the Root Port Interrupt FIFO overflowed and an
RW1C 0 interrupt message was dropped. Writing a 1 clears the overflow
status
RW 0 Sets the timeout counter size for Completion Timeouts.
RO 0 Reserved.
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Chapter 2: Product Specification
Description
Table 2-16).
Description
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