Axi Transactions For Pcie - Xilinx LogiCORE IP AXI Product Manual

Clocking Interface
Table 3-2 defines the clocking interface signals.
Table 3-2: Clocking Interface Signals
Name
pipe_pclk_in
pipe_rxusrclk_in
pipe_rxoutclk_in
pipe_dclk_in
pipe_userclk1_in
pipe_userclk2_in
pipe_mmcm_lock_in
pipe_txoutclk_out
pipe_rxoutclk_out
pipe_pclk_sel_out
pipe_gen3_out
pipe_mmcm_rst_n
The Clocking architecture is described in detail in the Use Model chapter of the 7 Series
FPGAs GTX/GTH Transceivers User Guide (UG476)

AXI Transactions for PCIe

Table 3-3 and Table 3-4
transactions.
Table 3-3: AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs
AXI4 Memory-Mapped Transaction
INCR Burst Read of 32-bit address AXIBAR
INCR Burst Write to 32-bit address AXIBAR
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Direction
Parallel clock used to synchronize data transfers across the
Input
parallel interface of the GTX transceiver.
Input Provides a clock for the internal RX PCS datapath.
Input Recommended clock output to the FPGA logic.
Input Dynamic reconfiguration clock.
Input Optional user clock.
Input Optional user clock.
Input Indicates if the MMCM is locked onto the source CLK.
Output Recommended clock output to the FPGA logic.
Output Recommended clock output to the FPGA logic.
Output Parallel clock select.
Output Indicates the PCI Express operating speed.
MMCM reset port. This port could be used by the upper layer to
reset MMCM if error recovery is required. If the system detects
the deassertion of MMCM lock, Xilinx recommends that you
reset the MMCM. The recommended approach is to reset the
MMCM after the MMCM input clock recovers (if MMCM reset
occurs before the input reference clock recovers, the MMCM
might never relock). After MMCM is reset, wait for MMCM to
lock and then reset the PIPE Wrapper as normally done.
Currently this port is tied High.
are the translation tables for AXI4-Stream and memory-mapped
www.xilinx.com
Chapter 3: Designing with the Core
Description
[Ref 3].
AXI4-Stream PCIe TLPs
MemRd 32 (3DW)
MemWr 32 (3DW)
50
Send Feedback